1. Technical Field
The present invention relates to sensing circuits in general, and in particular to charge amplifier circuits. Still more particularly, the present invention relates to an apparatus for reducing offset voltage drifts in a charge amplifier circuit.
2. Description of Related Art
Referring now to the drawings and in particular to FIG. 1, there is illustrated a schematic diagram of a charge amplifier circuit capable of converting the output of a piezoelectric charge mode sensor to a corresponding voltage, according to the prior art. As shown, a charge amplifier circuit 10 includes a piezoelectric sensor 11 that is capable of producing a charge proportional to an applied mechanical force. As the voltage at one of the inputs to an operational amplifier 12 begins to increase (or decrease) as a result of charge accumulation across a capacitor 14, the voltage at an output V0 of operational amplifier 12 will decrease (or increase) to maintain the voltage at the input of operational amplifier 12 at near 0 V. Thus, the voltage of output V0 is proportional to the charge output of piezoelectric sensor 11, and the virtual ground at the second input of operational amplifier 12 limits the charge lost due to parasitic capacitance and/or leakage in all cables within charge amplifier circuit 10.
The capacitance C1 of capacitor 14 determines the voltage at output V0 for a given amount of charges generated by piezoelectric sensor 11. Due to the input bias/offset current ib, a resistor 13 is utilized to drain the accumulated charges on capacitor 14. With resistor 13, operational amplifier 12 acts as a high-pass filter with a low-frequency cutoff at 1/(2πR1C1) where R1 is the resistance of resistor 13, and C1 is the capacitance of capacitor 14.
Because capacitor 14 requires a relatively small capacitance C1 to achieve a reasonable output voltage, one problem with charge amplifier circuit 10 is that the resistance R1 of resistor 13 must be very large in order to achieve a reasonable low-frequency cutoff. The input bias/offset current ib of operational amplifier 12 flowing over resistor 13 can cause a significant DC offset at output V0. In addition, the change in the input bias/offset current ib over temperature can also result in a significant offset drift at output V0. Even when using a JFET operational amplifier having an input bias/offset current and drift (per degree Celsius) in the pico range, the DC offset and offset drift (per degree Celsius) at output V0 can end up being in the milli range, which is unacceptably high for most, if not all, precision applications. Consequently, it would be desirable to provide an apparatus for reducing offset voltage drifts at the outputs of charge amplifier circuits.